Deep-Sleep Mode Clock Gating Control Register 1
| SYSCTL_DCGC1_UART0 | UART0 Clock Gating Control |
| SYSCTL_DCGC1_UART1 | UART1 Clock Gating Control |
| SYSCTL_DCGC1_UART2 | UART2 Clock Gating Control |
| SYSCTL_DCGC1_SSI0 | SSI0 Clock Gating Control |
| SYSCTL_DCGC1_SSI1 | SSI1 Clock Gating Control |
| SYSCTL_DCGC1_I2C0 | I2C0 Clock Gating Control |
| SYSCTL_DCGC1_I2C1 | I2C1 Clock Gating Control |
| SYSCTL_DCGC1_TIMER0 | Timer 0 Clock Gating Control |
| SYSCTL_DCGC1_TIMER1 | Timer 1 Clock Gating Control |
| SYSCTL_DCGC1_TIMER2 | Timer 2 Clock Gating Control |
| SYSCTL_DCGC1_TIMER3 | Timer 3 Clock Gating Control |
| SYSCTL_DCGC1_COMP0 | Analog Comparator 0 Clock Gating |
| SYSCTL_DCGC1_COMP1 | Analog Comparator 1 Clock Gating |